The advent of the integrated circuit has spawned the necessity for automated testing to achieve rapid, accurate, and high volume results. Accordingly, automated test equipment (ATE) has been developed to maximize integrated circuit test efficiency, while minimizing the amount of human intervention that is required to complete a particular set of test scenarios.
Typical ATEs include a so-called “device handler” for maneuvering each integrated circuit, or device under test (DUT), into position to allow a device tester to exercise the DUT using automated test sequences. More advanced ATEs provide the ability to implement test scenarios in parallel, whereby multiple DUTs may be exercised simultaneously. As such, multi-site motherboards have been developed to facilitate the placement of multiple DUTs on a single motherboard. The corresponding device testers employ a first set of test probes that are used to inject stimuli into the one or more input pins of each DUT, while a second set of test probes are used to measure each DUT's response to the test stimuli.
Device testers and device handlers, however, are generally allocated separately and are selected by the IC developer based upon the devices that are to be tested, which may vary widely in terms of package type, pin arrangement, and pin type. As such, a particular device tester/device handler pair may only be able to execute test scenarios on a very specific set of devices. Furthermore, compatibility between the device tester and device handler is further reduced when the DUTs are populated onto multi-site motherboards.
Such compatibility issues often force the IC developer to maintain an inventory of device tester/device handler pairs so as to accommodate the number of device types being tested by the IC developer. In addition, an inventory of DUT motherboards must also be maintained so as to accommodate compatibility between the inventory of device tester/device handler pairs. As such, a direct correlation exists between the costs imposed upon the IC developer and the number of device types that the IC developer wishes to test, since costs are increased in proportion to the number of device types that are to be tested.
Efforts continue, therefore, to develop interposers that reduce the costs imposed upon IC developers by reducing the number of device handler/device tester pairs and the number of DUT motherboards that must be maintained in inventory to accommodate the various IC device types that are to be tested.